1. Field of the Invention
The present invention relates to a semiconductor integrated circuit structure and semiconductor testing method thereof More specifically, the present invention relates to a test structure and testing method for quantifying damage resulting from plasma-etching during fabrication of semiconductor integrated circuits.
2. Description of the Related Art
The process of fabricating integrated circuits includes the deposition of multiple layers of semiconductor, dielectric, and conductive materials on a semiconductor wafer. Bach of the multiple layers is typically patterned and etched to form a useful pattern thereby creating and isolating active devices, capacitors, resistors, and the like. The patterning and etching further interconnects the active devices, capacitors, resistors, and the like to create an operational circuit. The material layers are commonly by chemical vapor deposited (CVD), growth, sputtering or evaporation. Etching is achieved by various wet etching and plasma etching processes. The deposition and etching steps are performed in a sequence wherein lower layers are covered by subsequently-deposited upper layers. The lower layers are therefore subjected to the physical effects that result from the deposition and etching steps for forming overlying structures. For example, an underlying layer is subjected to temperature changes inherent to deposition and annealing processes applied to upper layers. Furthermore, the etching of upper layers may damage or otherwise harmfully affect previously deposited, lower layers.
Plasma etching is a fabrication technique that is well known to cause damage to underlying structures. Plasma etching is any process using a plasma for generating reactive species that chemically etches material in direct proximity to the plasma. Plasma etching is known to cause damage to silicon substrate of an integrated circuit and also to other structures that are formed to produce operational circuits. For example, wafers that are etched by dry etch processes are typically subjected to contamination from multiple sources including polymeric residues from the etch process, deposition of nonvolatile contaminants from sputtering during the etch process, and particulate contamination. Polymeric residue contamination results from a halogen deficiency in halocarbon plasmas and may produce rough surfaces on etched films and underlayers, high contact resistance, and collection of corrosion-causing halogens.
What is needed is a technique for detecting and minimizing damage to the underlying layers of a semiconductor to improve reliability and performance of active devices such as MOS transistors.
Several methods of characterizing plasma-etch induced damage to silicon substrate and oxides have been employed. These methods include a determination of minority-carrier lifetime which is commonly called wafer tau(.tau.) surface photo-voltage measurements (SPV) for measuring minority carrier lifetime of the surface region of a semiconductor to detect damage to the semiconductor substrate material, thermal wave measurements for detecting changed reflectivity characteristics caused by damage, and standard diode leakage measurements. Other methods include breakdown measurements on blanket (unpatterned) wafers to detect damage to the oxide layer resulting from general exposure to the etchant, and electron microscopy (SEM/TEM) cross-section analysis to visually detect trenching. All methods are capable of measuring plasma-induced damage to some extent, but all have limitations including a limited sensitivity. Furthermore, the conventional test techniques supply only general damage estimates that are inadequate for evaluating advanced small-geometry processes due to an overall lack of sensitivity and a limited capability to resolve areas between closely-spaced devices. In addition, many of the techniques involve destructive testing and are therefore inadequate for testing production devices.
For example, breakdown measurements on an unpatterned wafer offer no insight into plasma-etch effects on actual active devices and the oxide layer weaknesses that are common to etched structures. Surface photo-voltage measurements permit an inference of damage to the silicon but do not specifically resolve damage at the edges of an etched structure. Electron microscopy is a destructive analysis that requires cross-sectioning of the integrated circuit so that only damage to the oxide located along the sampled cross-section is detected.
What is needed is a non-destructive test technique and test structure for characterizing plasma-induced damage that is simple, integrates easily and inexpensively into an integrated circuit process flow, and generates a highly sensitive characterization of damage.